1. Field of Use
The present invention relates to data processing systems and more particularly to cache memory systems.
2. Prior Art
It is well known to provide hierarchal memory organizations in which a large slow speed main memory operates in conjunction with a small high speed buffer storage unit or cache. In such arrangements, the central processing unit (CPU) can access operand data and/or instructions at a rate which more closely approximates the machine. During normal operation, when the CPU provides the address of the information to be accessed, control circuits perform a search of a directory which stores associative addresses for specifying which blocks of information reside in cache (i.e., define hit condition). When it determines that the information resides in cache, the information is accessed and transferred to the CPU. When the requested information is not in cache, the control circuits request the information from main memory and upon its receipt write the information into cache at which time it may be accessed.
Examples of such systems are disclosed in the referenced patent applications of Charles P. Ryan and in U.S. Pat. No. 3,588,829. In the system disclosed in the Ryan applications, the cache includes four levels which were addressed by the same set of address signals for accessing of four words of a block of instructions or data.
Since memory data must be processed on a real time basis, the writing of memory data normally interferes with such accessing of instructions. To overcome such interference, prior art arrangements hold up processor operations until the memory data is written into cache. This has been found to limit the overall access rate of the CPU resulting in a decrease in CPU performance.
Accordingly, it is a primary object of the present invention to provide a cache arrangement which provides a central processing unit with rapid access to information.
It is a further object of the present invention to provide a cache arrangement which permits the execution of concurrent operations.